1. Field of the Invention
The invention relates to an apparatus and method for fabricating a metal layer on a substrate, and more particularly, to an apparatus for electrochemical deposition with auxiliary cathode, conductive layer on a semiconductor wafer and a fabrication method for the same.
2. Description of the Related Art
Conductive interconnections on integrated circuits conventionally take the form of trenches and vias. In deep submicron integrated circuits, the trenches and vias are typically formed by a damascene or dual damascene process. Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to lower resistivity and better electromigration resistance. Electrochemical copper deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electroplating is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
FIG. 1 shows a conventional electrochemical plating process apparatus 100, with a wafer 2 mounted therein. Apparatus 100 includes a substrate holder assembly 3 mounted on a rotatable spindle 5. During the electrochemical plating cycle, semiconductor wafer 2 is mounted on the substrate holder assembly 3, which is then placed in a plating bath 22 containing a plating solution. As indicated by arrow 13, the plating solution is continually applied by a pump 40, flowing upwards to the center of the wafer and then radically outward and across wafer 2, as indicated by arrows 14. The plating solution then overflows from plating bath 22 to an overflow reservoir 20 as indicated by arrows 10 and 11. The plating solution is then filtered (not shown) and returned to pump 40 as indicated by arrow 12, completing recirculation. A DC power supply 50 has a negative output lead electrically connected to wafer 2. The positive output lead of power supply 50 is electrically connected to an anode 1 located in plating bath 22. During use, power supply 50 biases wafer 2 to provide a negative potential relative to anode 1 generating electrical current from the anode 1 to wafer 2.
FIG. 2 is a schematic view of an electric flux line between the anode and cathode of the conventional electrochemical plating process apparatus. In FIG. 2, a semiconductor wafer 2 is mounted on the substrate holder assembly 3. A contact ring 25 electrically connects the semiconductor wafer 2 through contact pins 25a. When an electrical field is biased between the anode 1 and the semiconductor wafer (cathode) 2, a plurality of field lines Fc and Fe show potential drop between the anode and cathode. Since the contact ring 25 electrically connects the semiconductor wafer 2 through contact pins 25a, sharper potential drop occurs at the circumference of the semiconductor such that the flux density Fe adjacent to the contact pins is more focused than the flux density Fc at the center region of cathode. The higher flux density Fe adjacent to the contact pins results in higher current density as well as thicker deposition, thereby inducing peeling and particle sources due to edge residue. Uneven thickness can also exacerbate abnormal process performance and high resistance deviation performance.
Moreover, even though the film is planarized by CMP, copper residue can still be found on the wafer edge. Therefore, it is important that the electroplating surface is uniform and reliable to ensure edge residue free deposition.
However, it remains difficult to eliminate all edge residue and uneven plating thickness during ECD.